Silego被德勤认为是在硅谷发展迅猛的前50的科技公司之一。Silego开发硅芯片解决方案,以减少元件数量,功耗和成本,是在硅谷增长最快的半导体公司之一。
Silego是全球的笔记本电脑和上网本时钟供应商,拥有大量的产品线,涵盖DDR3寄存器集成电路,消费性产品,笔记本电脑和上网本芯片。 Silego总部位于加利福尼亚州圣克拉拉,其业务和设计中心遍及全球。Silego科技是一家私人持有的并获得的风险投资公司支持的公司。
二、招聘职位
Job Description:
This position will participate in layout design team for analog and mixed signal circuits on CMOS process. Work through entire chip construction process, from preliminary floor planning, detailed sub-block layout, and global placement and routing. Responsible for running full verification sequence using advanced EDA tools. The responsibilities will include but not limited to:
Layout floor planning of large, mixed signal IC
Transistor level sub-block layout based on schematics provide by designers, including careful analog considerations
Verifying and completing the IC with DRC/LVS checks, chip-finishing and bonding
Delivering back-annotated data needed for timing verification of modules, both standalone and embedded in top level circuitry
Job Requirement:
BSEE or above, MSEE preferred
Be able to translate circuits schematics directly to layout
Understand IC process basics
Understand circuit basics and how they impact IC layout strategy
Very good communication skills in English and Chinese
工作地点:合肥
工作经验:应届毕业生
最低学历:本科
专业要求:微电子相关专业(应用物理 电子科学与技术 微电子学)
招聘人数:1人
薪资福利:年薪8万左右,五险一金,双休
三、联系方式
联系方式:0551-65368431,简历请投至 xli@silego.com
公司地址:安徽省合肥市天元路3号留学生园2号楼303